Since the invention of the single transistor dynamic memory cell, the basic rule of one transistor and one capacitor per stored bit has not changed. In order to pack more bits per unit of silicon area, more sophisticated lithographic equipment and methods are continuously being developed and used to fabricate these memory devices. Another way to achieve better density is to store more than one data bit per single memory cell. This is known commonly as multi-level cell memory. Prior art patents that discuss multi-level storage in dynamic semiconductor memory include U.S. Pat. No 5,293,563 of Ohta for MULTI-LEVEL MEMORY CELL WITH INCREASED READ-OUT MARGIN ("Ohta"). Ohta describes a dynamic semiconductor memory device using a memory cell consisting of two (2) transistors and a capacitor to store two bits of digital data. The result is a memory device using one and one-half (1.5) elements instead of two (2) elements per bit of storage. Ohta provides an enhanced cell signal storage with complementary polarities applied to the memory cell. One major disadvantage of the cell is its layout difficulty which results in larger than expected actual cell size.
U.S. Pat. No. 5,283,761 of Gillingham entitled METHOD OF MULTI-LEVEL STORAGE IN DRAM ("Gillingham") describes a DRAM memory cell capable of storing four (4) voltage levels. To do this, Gillingham subdivides the bit line, uses about six (6) precharge and equalizing clocks involving complex and difficult to generate clock timings (including some precharge and isolation clocks twice activated in a single cycle), and a dummy word line. The bit line sections also have to be charged, equalized and discharged twice in a single cycle, resulting in a slow memory device, not suitable for high speed dynamic operation in high density DRAMs.